/*-------------------------------- Arctic Core ------------------------------
 * Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
 * Contact: <contact@arccore.com>
 *
 * You may ONLY use this file:
 * 1)if you have a valid commercial ArcCore license and then in accordance with
 * the terms contained in the written license agreement between you and ArcCore,
 * or alternatively
 * 2)if you follow the terms found in GNU General Public License version 2 as
 * published by the Free Software Foundation and appearing in the file
 * LICENSE.GPL included in the packaging of this file or here
 * <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
 *-------------------------------- Arctic Core -----------------------------*/

#ifndef IRQ_TC297_H_
#define IRQ_TC297_H_



#define IRQ_OFFSET(_x)  ((_x)/4uL)

#define IRQ_SRC_CPU0SBSRC       IRQ_OFFSET(0x0000uL)
#define IRQ_SRC_CPU1SBSRC       IRQ_OFFSET(0x0004uL)
#define IRQ_SRC_CPU2SBSRC       IRQ_OFFSET(0x0008uL)
#define IRQ_SRC_EMEM            IRQ_OFFSET(0x0020uL)
#define IRQ_SRC_AGBT            IRQ_OFFSET(0x0024uL)
#define IRQ_SRC_BCUSPBSBSRC     IRQ_OFFSET(0x0040uL)
#define IRQ_SRC_XBARSRC         IRQ_OFFSET(0x0048uL)
#define IRQ_SRC_Cerberus0       IRQ_OFFSET(0x0050uL)
#define IRQ_SRC_Cerberus1       IRQ_OFFSET(0x0054uL)
#define IRQ_SRC_ASCLIN0TX       IRQ_OFFSET(0x0080uL)
#define IRQ_SRC_ASCLIN1TX       IRQ_OFFSET(0x008CuL)
#define IRQ_SRC_ASCLIN2TX       IRQ_OFFSET(0x0098uL)
#define IRQ_SRC_ASCLIN3TX       IRQ_OFFSET(0x00A4uL)
#define IRQ_SRC_ASCLIN0RX       IRQ_OFFSET(0x0084uL)
#define IRQ_SRC_ASCLIN1RX       IRQ_OFFSET(0x0090uL)
#define IRQ_SRC_ASCLIN2RX       IRQ_OFFSET(0x009CuL)
#define IRQ_SRC_ASCLIN3RX       IRQ_OFFSET(0x00A8uL)
#define IRQ_SRC_ASCLIN0EX       IRQ_OFFSET(0x0088uL)
#define IRQ_SRC_ASCLIN1EX       IRQ_OFFSET(0x0094uL)
#define IRQ_SRC_ASCLIN2EX       IRQ_OFFSET(0x00A0uL)
#define IRQ_SRC_ASCLIN3EX       IRQ_OFFSET(0x00ACuL)
#define IRQ_SRC_QSPI0TX         IRQ_OFFSET(0x0190uL)
#define IRQ_SRC_QSPI1TX         IRQ_OFFSET(0x01A8uL)
#define IRQ_SRC_QSPI2TX         IRQ_OFFSET(0x01C0uL)
#define IRQ_SRC_QSPI3TX         IRQ_OFFSET(0x01D8uL)
#define IRQ_SRC_QSPI4TX         IRQ_OFFSET(0x01F0uL)
#define IRQ_SRC_QSPI5TX         IRQ_OFFSET(0x0208uL)
#define IRQ_SRC_QSPI0RX         IRQ_OFFSET(0x0194uL)
#define IRQ_SRC_QSPI1RX         IRQ_OFFSET(0x01ACuL)
#define IRQ_SRC_QSPI2RX         IRQ_OFFSET(0x01C4uL)
#define IRQ_SRC_QSPI3RX         IRQ_OFFSET(0x01DCuL)
#define IRQ_SRC_QSPI4RX         IRQ_OFFSET(0x01F4uL)
#define IRQ_SRC_QSPI5RX         IRQ_OFFSET(0x020CuL)
#define IRQ_SRC_QSPI0ERR        IRQ_OFFSET(0x0198uL)
#define IRQ_SRC_QSPI1ERR        IRQ_OFFSET(0x01B0uL)
#define IRQ_SRC_QSPI2ERR        IRQ_OFFSET(0x01C8uL)
#define IRQ_SRC_QSPI3ERR        IRQ_OFFSET(0x01E0uL)
#define IRQ_SRC_QSPI4ERR        IRQ_OFFSET(0x01F8uL)
#define IRQ_SRC_QSPI5ERR        IRQ_OFFSET(0x0210uL)
#define IRQ_SRC_QSPI0PT         IRQ_OFFSET(0x019CuL)
#define IRQ_SRC_QSPI1PT         IRQ_OFFSET(0x01B4uL)
#define IRQ_SRC_QSPI2PT         IRQ_OFFSET(0x01CCuL)
#define IRQ_SRC_QSPI3PT         IRQ_OFFSET(0x01E4uL)
#define IRQ_SRC_QSPI4PT         IRQ_OFFSET(0x01FCuL)
#define IRQ_SRC_QSPI5PT         IRQ_OFFSET(0x0214uL)
#define IRQ_SRC_QSPI2HC         IRQ_OFFSET(0x01A0uL+(2 * 0x18uL))
#define IRQ_SRC_QSPI3HC         IRQ_OFFSET(0x01A0uL+(3 * 0x18uL))
#define IRQ_SRC_QSPI0U          IRQ_OFFSET(0x01A4uL+(0 * 0x18uL))
#define IRQ_SRC_QSPI1U          IRQ_OFFSET(0x01A4uL+(1 * 0x18uL))
#define IRQ_SRC_QSPI2U          IRQ_OFFSET(0x01A4uL+(2 * 0x18uL))
#define IRQ_SRC_QSPI3U          IRQ_OFFSET(0x01A4uL+(3 * 0x18uL))
#define IRQ_SRC_QSPI4U          IRQ_OFFSET(0x01A4uL+(4 * 0x18uL))
#define IRQ_SRC_QSPI5U          IRQ_OFFSET(0x01A4uL+(5 * 0x18uL))
#define IRQ_SRC_HSCT            IRQ_OFFSET(0x0290uL)
#define IRQ_SRC_HSSLCOK0        IRQ_OFFSET(0x02A0uL+(0 * 0x10uL))
#define IRQ_SRC_HSSLCOK1        IRQ_OFFSET(0x02A0uL+(1 * 0x10uL))
#define IRQ_SRC_HSSLCOK2        IRQ_OFFSET(0x02A0uL+(2 * 0x10uL))
#define IRQ_SRC_HSSLCOK3        IRQ_OFFSET(0x02A0uL+(3 * 0x10uL))
#define IRQ_SRC_HSSLRDI0        IRQ_OFFSET(0x02A4uL+(0 * 0x10uL))
#define IRQ_SRC_HSSLRDI1        IRQ_OFFSET(0x02A4uL+(1 * 0x10uL))
#define IRQ_SRC_HSSLRDI2        IRQ_OFFSET(0x02A4uL+(2 * 0x10uL))
#define IRQ_SRC_HSSLRDI3        IRQ_OFFSET(0x02A4uL+(3 * 0x10uL))
#define IRQ_SRC_HSSLERR0        IRQ_OFFSET(0x02A8uL+(0 * 0x10uL))
#define IRQ_SRC_HSSLERR1        IRQ_OFFSET(0x02A8uL+(1 * 0x10uL))
#define IRQ_SRC_HSSLERR2        IRQ_OFFSET(0x02A8uL+(2 * 0x10uL))
#define IRQ_SRC_HSSLERR3        IRQ_OFFSET(0x02A8uL+(3 * 0x10uL))
#define IRQ_SRC_HSSLTRG0        IRQ_OFFSET(0x02ACuL+(0 * 0x10uL))
#define IRQ_SRC_HSSLTRG1        IRQ_OFFSET(0x02ACuL+(1 * 0x10uL))
#define IRQ_SRC_HSSLTRG2        IRQ_OFFSET(0x02ACuL+(2 * 0x10uL))
#define IRQ_SRC_HSSLTRG3        IRQ_OFFSET(0x02ACuL+(3 * 0x10uL))
#define IRQ_SRC_HSSLEXI         IRQ_OFFSET(0x02E0uL)
#define IRQ_SRC_I2C0BREQ        IRQ_OFFSET(0x0300uL)
#define IRQ_SRC_I2C0LBREQ       IRQ_OFFSET(0x0304uL)
#define IRQ_SRC_I2C0SREQ        IRQ_OFFSET(0x0308uL)
#define IRQ_SRC_I2C0LSREQ       IRQ_OFFSET(0x030CuL)
#define IRQ_SRC_I2C0ERR         IRQ_OFFSET(0x0310uL)
#define IRQ_SRC_I2C0P           IRQ_OFFSET(0x0314uL)
#define IRQ_SRC_I2C1BREQ        IRQ_OFFSET(0x0318uL)
#define IRQ_SRC_I2C1LBREQ       IRQ_OFFSET(0x031CuL)
#define IRQ_SRC_I2C1SREQ        IRQ_OFFSET(0x0320uL)
#define IRQ_SRC_I2C1LSREQ       IRQ_OFFSET(0x0324uL)
#define IRQ_SRC_I2C1ERR         IRQ_OFFSET(0x0328uL)
#define IRQ_SRC_I2C1P           IRQ_OFFSET(0x032CuL)
#define IRQ_SRC_SENT0           IRQ_OFFSET(0x0350uL+(0 * 0x4uL))
#define IRQ_SRC_SENT1           IRQ_OFFSET(0x0350uL+(1 * 0x4uL))
#define IRQ_SRC_SENT2           IRQ_OFFSET(0x0350uL+(2 * 0x4uL))
#define IRQ_SRC_SENT3           IRQ_OFFSET(0x0350uL+(3 * 0x4uL))
#define IRQ_SRC_SENT4           IRQ_OFFSET(0x0350uL+(4 * 0x4uL))
#define IRQ_SRC_SENT5           IRQ_OFFSET(0x0350uL+(5 * 0x4uL))
#define IRQ_SRC_SENT6           IRQ_OFFSET(0x0350uL+(6 * 0x4uL))
#define IRQ_SRC_SENT7           IRQ_OFFSET(0x0350uL+(7 * 0x4uL))
#define IRQ_SRC_SENT8           IRQ_OFFSET(0x0350uL+(8 * 0x4uL))
#define IRQ_SRC_SENT9           IRQ_OFFSET(0x0350uL+(9 * 0x4uL))
#define IRQ_SRC_SENT10          IRQ_OFFSET(0x0350uL+(10 * 0x4uL))
#define IRQ_SRC_SENT11          IRQ_OFFSET(0x0350uL+(11 * 0x4uL))
#define IRQ_SRC_SENT12          IRQ_OFFSET(0x0350uL+(12 * 0x4uL))
#define IRQ_SRC_SENT13          IRQ_OFFSET(0x0350uL+(13 * 0x4uL))
#define IRQ_SRC_SENT14          IRQ_OFFSET(0x0350uL+(14 * 0x4uL))
#define IRQ_SRC_MSC0SR0         IRQ_OFFSET(0x03E0uL+(0 * 0x14uL))
#define IRQ_SRC_MSC1SR0         IRQ_OFFSET(0x03E0uL+(1 * 0x14uL))
#define IRQ_SRC_MSC2SR0         IRQ_OFFSET(0x03E0uL+(2 * 0x14uL))
#define IRQ_SRC_MSC0SR1         IRQ_OFFSET(0x03E4uL+(0 * 0x14uL))
#define IRQ_SRC_MSC1SR1         IRQ_OFFSET(0x03E4uL+(1 * 0x14uL))
#define IRQ_SRC_MSC2SR1         IRQ_OFFSET(0x03E4uL+(2 * 0x14uL))
#define IRQ_SRC_MSC0SR2         IRQ_OFFSET(0x03E8uL+(0 * 0x14uL))
#define IRQ_SRC_MSC1SR2         IRQ_OFFSET(0x03E8uL+(1 * 0x14uL))
#define IRQ_SRC_MSC2SR2         IRQ_OFFSET(0x03E8uL+(2 * 0x14uL))
#define IRQ_SRC_MSC0SR3         IRQ_OFFSET(0x03ECuL+(0 * 0x14uL))
#define IRQ_SRC_MSC1SR3         IRQ_OFFSET(0x03ECuL+(1 * 0x14uL))
#define IRQ_SRC_MSC2SR3         IRQ_OFFSET(0x03ECuL+(2 * 0x14uL))
#define IRQ_SRC_MSC0SR4         IRQ_OFFSET(0x03F0uL+(0 * 0x14uL))
#define IRQ_SRC_MSC1SR4         IRQ_OFFSET(0x03F0uL+(1 * 0x14uL))
#define IRQ_SRC_MSC2SR4         IRQ_OFFSET(0x03F0uL+(2 * 0x14uL))
#define IRQ_SRC_CCU60SR0        IRQ_OFFSET(0x0420uL+(0 * 0x10uL))
#define IRQ_SRC_CCU61SR0        IRQ_OFFSET(0x0420uL+(1 * 0x10uL))
#define IRQ_SRC_CCU60SR1        IRQ_OFFSET(0x0424uL+(0 * 0x10uL))
#define IRQ_SRC_CCU61SR1        IRQ_OFFSET(0x0424uL+(1 * 0x10uL))
#define IRQ_SRC_CCU60SR2        IRQ_OFFSET(0x0428uL+(0 * 0x10uL))
#define IRQ_SRC_CCU61SR2        IRQ_OFFSET(0x0428uL+(1 * 0x10uL))
#define IRQ_SRC_CCU60SR3        IRQ_OFFSET(0x042CuL+(0 * 0x10uL))
#define IRQ_SRC_CCU61SR3        IRQ_OFFSET(0x042CuL+(1 * 0x10uL))
#define IRQ_SRC_GPT120CIRQ      IRQ_OFFSET(0x0460uL)
#define IRQ_SRC_GPT120T2        IRQ_OFFSET(0x0464uL)
#define IRQ_SRC_GPT120T3        IRQ_OFFSET(0x0468uL)
#define IRQ_SRC_GPT120T4        IRQ_OFFSET(0x046CuL)
#define IRQ_SRC_GPT120T5        IRQ_OFFSET(0x0470uL)
#define IRQ_SRC_GPT120T6        IRQ_OFFSET(0x0474uL)
#define IRQ_SRC_STM0SR0         IRQ_OFFSET(0x0490uL+(0 * 0x8uL))
#define IRQ_SRC_STM1SR0         IRQ_OFFSET(0x0490uL+(1 * 0x8uL))
#define IRQ_SRC_STM2SR0         IRQ_OFFSET(0x0490uL+(2 * 0x8uL))
#define IRQ_SRC_STM0SR1         IRQ_OFFSET(0x0494uL+(0 * 0x8uL))
#define IRQ_SRC_STM1SR1         IRQ_OFFSET(0x0494uL+(1 * 0x8uL))
#define IRQ_SRC_STM2SR1         IRQ_OFFSET(0x0494uL+(2 * 0x8uL))
#define IRQ_SRC_FCE             IRQ_OFFSET(0x04B0uL)
#define IRQ_SRC_DMAERR          IRQ_OFFSET(0x04F0uL)
#define IRQ_SRC_DMACH0          IRQ_OFFSET(0x0500uL+(0 * 0x4uL))
#define IRQ_SRC_DMACH1          IRQ_OFFSET(0x0500uL+(1 * 0x4uL))
#define IRQ_SRC_DMACH2          IRQ_OFFSET(0x0500uL+(2 * 0x4uL))
#define IRQ_SRC_DMACH3          IRQ_OFFSET(0x0500uL+(3 * 0x4uL))
#define IRQ_SRC_DMACH4          IRQ_OFFSET(0x0500uL+(4 * 0x4uL))
#define IRQ_SRC_DMACH5          IRQ_OFFSET(0x0500uL+(5 * 0x4uL))
#define IRQ_SRC_DMACH6          IRQ_OFFSET(0x0500uL+(6 * 0x4uL))
#define IRQ_SRC_DMACH7          IRQ_OFFSET(0x0500uL+(7 * 0x4uL))
#define IRQ_SRC_DMACH8          IRQ_OFFSET(0x0500uL+(8 * 0x4uL))
#define IRQ_SRC_DMACH9          IRQ_OFFSET(0x0500uL+(9 * 0x4uL))
#define IRQ_SRC_DMACH10         IRQ_OFFSET(0x0500uL+(10 * 0x4uL))
#define IRQ_SRC_DMACH11         IRQ_OFFSET(0x0500uL+(11 * 0x4uL))
#define IRQ_SRC_DMACH12         IRQ_OFFSET(0x0500uL+(12 * 0x4uL))
#define IRQ_SRC_DMACH13         IRQ_OFFSET(0x0500uL+(13 * 0x4uL))
#define IRQ_SRC_DMACH14         IRQ_OFFSET(0x0500uL+(14 * 0x4uL))
#define IRQ_SRC_DMACH15         IRQ_OFFSET(0x0500uL+(15 * 0x4uL))
#define IRQ_SRC_DMACH16         IRQ_OFFSET(0x0500uL+(16 * 0x4uL))
#define IRQ_SRC_DMACH17         IRQ_OFFSET(0x0500uL+(17 * 0x4uL))
#define IRQ_SRC_DMACH18         IRQ_OFFSET(0x0500uL+(18 * 0x4uL))
#define IRQ_SRC_DMACH19         IRQ_OFFSET(0x0500uL+(19 * 0x4uL))
#define IRQ_SRC_DMACH20         IRQ_OFFSET(0x0500uL+(20 * 0x4uL))
#define IRQ_SRC_DMACH21         IRQ_OFFSET(0x0500uL+(21 * 0x4uL))
#define IRQ_SRC_DMACH22         IRQ_OFFSET(0x0500uL+(22 * 0x4uL))
#define IRQ_SRC_DMACH23         IRQ_OFFSET(0x0500uL+(23 * 0x4uL))
#define IRQ_SRC_DMACH24         IRQ_OFFSET(0x0500uL+(24 * 0x4uL))
#define IRQ_SRC_DMACH25         IRQ_OFFSET(0x0500uL+(25 * 0x4uL))
#define IRQ_SRC_DMACH26         IRQ_OFFSET(0x0500uL+(26 * 0x4uL))
#define IRQ_SRC_DMACH27         IRQ_OFFSET(0x0500uL+(27 * 0x4uL))
#define IRQ_SRC_DMACH28         IRQ_OFFSET(0x0500uL+(28 * 0x4uL))
#define IRQ_SRC_DMACH29         IRQ_OFFSET(0x0500uL+(29 * 0x4uL))
#define IRQ_SRC_DMACH30         IRQ_OFFSET(0x0500uL+(30 * 0x4uL))
#define IRQ_SRC_DMACH31         IRQ_OFFSET(0x0500uL+(31 * 0x4uL))
#define IRQ_SRC_DMACH32         IRQ_OFFSET(0x0500uL+(32 * 0x4uL))
#define IRQ_SRC_DMACH33         IRQ_OFFSET(0x0500uL+(33 * 0x4uL))
#define IRQ_SRC_DMACH34         IRQ_OFFSET(0x0500uL+(34 * 0x4uL))
#define IRQ_SRC_DMACH35         IRQ_OFFSET(0x0500uL+(35 * 0x4uL))
#define IRQ_SRC_DMACH36         IRQ_OFFSET(0x0500uL+(36 * 0x4uL))
#define IRQ_SRC_DMACH37         IRQ_OFFSET(0x0500uL+(37 * 0x4uL))
#define IRQ_SRC_DMACH38         IRQ_OFFSET(0x0500uL+(38 * 0x4uL))
#define IRQ_SRC_DMACH39         IRQ_OFFSET(0x0500uL+(39 * 0x4uL))
#define IRQ_SRC_DMACH40         IRQ_OFFSET(0x0500uL+(40 * 0x4uL))
#define IRQ_SRC_DMACH41         IRQ_OFFSET(0x0500uL+(41 * 0x4uL))
#define IRQ_SRC_DMACH42         IRQ_OFFSET(0x0500uL+(42 * 0x4uL))
#define IRQ_SRC_DMACH43         IRQ_OFFSET(0x0500uL+(43 * 0x4uL))
#define IRQ_SRC_DMACH44         IRQ_OFFSET(0x0500uL+(44 * 0x4uL))
#define IRQ_SRC_DMACH45         IRQ_OFFSET(0x0500uL+(45 * 0x4uL))
#define IRQ_SRC_DMACH46         IRQ_OFFSET(0x0500uL+(46 * 0x4uL))
#define IRQ_SRC_DMACH47         IRQ_OFFSET(0x0500uL+(47 * 0x4uL))
#define IRQ_SRC_DMACH48         IRQ_OFFSET(0x0500uL+(48 * 0x4uL))
#define IRQ_SRC_DMACH49         IRQ_OFFSET(0x0500uL+(49 * 0x4uL))
#define IRQ_SRC_DMACH50         IRQ_OFFSET(0x0500uL+(50 * 0x4uL))
#define IRQ_SRC_DMACH51         IRQ_OFFSET(0x0500uL+(51 * 0x4uL))
#define IRQ_SRC_DMACH52         IRQ_OFFSET(0x0500uL+(52 * 0x4uL))
#define IRQ_SRC_DMACH53         IRQ_OFFSET(0x0500uL+(53 * 0x4uL))
#define IRQ_SRC_DMACH54         IRQ_OFFSET(0x0500uL+(54 * 0x4uL))
#define IRQ_SRC_DMACH55         IRQ_OFFSET(0x0500uL+(55 * 0x4uL))
#define IRQ_SRC_DMACH56         IRQ_OFFSET(0x0500uL+(56 * 0x4uL))
#define IRQ_SRC_DMACH57         IRQ_OFFSET(0x0500uL+(57 * 0x4uL))
#define IRQ_SRC_DMACH58         IRQ_OFFSET(0x0500uL+(58 * 0x4uL))
#define IRQ_SRC_DMACH59         IRQ_OFFSET(0x0500uL+(59 * 0x4uL))
#define IRQ_SRC_DMACH60         IRQ_OFFSET(0x0500uL+(60 * 0x4uL))
#define IRQ_SRC_DMACH61         IRQ_OFFSET(0x0500uL+(61 * 0x4uL))
#define IRQ_SRC_DMACH62         IRQ_OFFSET(0x0500uL+(62 * 0x4uL))
#define IRQ_SRC_DMACH63         IRQ_OFFSET(0x0500uL+(63 * 0x4uL))
#define IRQ_SRC_DMACH64         IRQ_OFFSET(0x0500uL+(64 * 0x4uL))
#define IRQ_SRC_DMACH65         IRQ_OFFSET(0x0500uL+(65 * 0x4uL))
#define IRQ_SRC_DMACH66         IRQ_OFFSET(0x0500uL+(66 * 0x4uL))
#define IRQ_SRC_DMACH67         IRQ_OFFSET(0x0500uL+(67 * 0x4uL))
#define IRQ_SRC_DMACH68         IRQ_OFFSET(0x0500uL+(68 * 0x4uL))
#define IRQ_SRC_DMACH69         IRQ_OFFSET(0x0500uL+(69 * 0x4uL))
#define IRQ_SRC_DMACH70         IRQ_OFFSET(0x0500uL+(70 * 0x4uL))
#define IRQ_SRC_DMACH71         IRQ_OFFSET(0x0500uL+(71 * 0x4uL))
#define IRQ_SRC_DMACH72         IRQ_OFFSET(0x0500uL+(72 * 0x4uL))
#define IRQ_SRC_DMACH73         IRQ_OFFSET(0x0500uL+(73 * 0x4uL))
#define IRQ_SRC_DMACH74         IRQ_OFFSET(0x0500uL+(74 * 0x4uL))
#define IRQ_SRC_DMACH75         IRQ_OFFSET(0x0500uL+(75 * 0x4uL))
#define IRQ_SRC_DMACH76         IRQ_OFFSET(0x0500uL+(76 * 0x4uL))
#define IRQ_SRC_DMACH77         IRQ_OFFSET(0x0500uL+(77 * 0x4uL))
#define IRQ_SRC_DMACH78         IRQ_OFFSET(0x0500uL+(78 * 0x4uL))
#define IRQ_SRC_DMACH79         IRQ_OFFSET(0x0500uL+(79 * 0x4uL))
#define IRQ_SRC_DMACH80         IRQ_OFFSET(0x0500uL+(80 * 0x4uL))
#define IRQ_SRC_DMACH81         IRQ_OFFSET(0x0500uL+(81 * 0x4uL))
#define IRQ_SRC_DMACH82         IRQ_OFFSET(0x0500uL+(82 * 0x4uL))
#define IRQ_SRC_DMACH83         IRQ_OFFSET(0x0500uL+(83 * 0x4uL))
#define IRQ_SRC_DMACH84         IRQ_OFFSET(0x0500uL+(84 * 0x4uL))
#define IRQ_SRC_DMACH85         IRQ_OFFSET(0x0500uL+(85 * 0x4uL))
#define IRQ_SRC_DMACH86         IRQ_OFFSET(0x0500uL+(86 * 0x4uL))
#define IRQ_SRC_DMACH87         IRQ_OFFSET(0x0500uL+(87 * 0x4uL))
#define IRQ_SRC_DMACH88         IRQ_OFFSET(0x0500uL+(88 * 0x4uL))
#define IRQ_SRC_DMACH89         IRQ_OFFSET(0x0500uL+(89 * 0x4uL))
#define IRQ_SRC_DMACH90         IRQ_OFFSET(0x0500uL+(90 * 0x4uL))
#define IRQ_SRC_DMACH91         IRQ_OFFSET(0x0500uL+(91 * 0x4uL))
#define IRQ_SRC_DMACH92         IRQ_OFFSET(0x0500uL+(92 * 0x4uL))
#define IRQ_SRC_DMACH93         IRQ_OFFSET(0x0500uL+(93 * 0x4uL))
#define IRQ_SRC_DMACH94         IRQ_OFFSET(0x0500uL+(94 * 0x4uL))
#define IRQ_SRC_DMACH95         IRQ_OFFSET(0x0500uL+(95 * 0x4uL))
#define IRQ_SRC_DMACH96         IRQ_OFFSET(0x0500uL+(96 * 0x4uL))
#define IRQ_SRC_DMACH97         IRQ_OFFSET(0x0500uL+(97 * 0x4uL))
#define IRQ_SRC_DMACH98         IRQ_OFFSET(0x0500uL+(98 * 0x4uL))
#define IRQ_SRC_DMACH99         IRQ_OFFSET(0x0500uL+(99 * 0x4uL))
#define IRQ_SRC_DMACH100        IRQ_OFFSET(0x0500uL+(100 * 0x4uL))
#define IRQ_SRC_DMACH101        IRQ_OFFSET(0x0500uL+(101 * 0x4uL))
#define IRQ_SRC_DMACH102        IRQ_OFFSET(0x0500uL+(102 * 0x4uL))
#define IRQ_SRC_DMACH103        IRQ_OFFSET(0x0500uL+(103 * 0x4uL))
#define IRQ_SRC_DMACH104        IRQ_OFFSET(0x0500uL+(104 * 0x4uL))
#define IRQ_SRC_DMACH105        IRQ_OFFSET(0x0500uL+(105 * 0x4uL))
#define IRQ_SRC_DMACH106        IRQ_OFFSET(0x0500uL+(106 * 0x4uL))
#define IRQ_SRC_DMACH107        IRQ_OFFSET(0x0500uL+(107 * 0x4uL))
#define IRQ_SRC_DMACH108        IRQ_OFFSET(0x0500uL+(108 * 0x4uL))
#define IRQ_SRC_DMACH109        IRQ_OFFSET(0x0500uL+(109 * 0x4uL))
#define IRQ_SRC_DMACH110        IRQ_OFFSET(0x0500uL+(110 * 0x4uL))
#define IRQ_SRC_DMACH111        IRQ_OFFSET(0x0500uL+(111 * 0x4uL))
#define IRQ_SRC_DMACH112        IRQ_OFFSET(0x0500uL+(112 * 0x4uL))
#define IRQ_SRC_DMACH113        IRQ_OFFSET(0x0500uL+(113 * 0x4uL))
#define IRQ_SRC_DMACH114        IRQ_OFFSET(0x0500uL+(114 * 0x4uL))
#define IRQ_SRC_DMACH115        IRQ_OFFSET(0x0500uL+(115 * 0x4uL))
#define IRQ_SRC_DMACH116        IRQ_OFFSET(0x0500uL+(116 * 0x4uL))
#define IRQ_SRC_DMACH117        IRQ_OFFSET(0x0500uL+(117 * 0x4uL))
#define IRQ_SRC_DMACH118        IRQ_OFFSET(0x0500uL+(118 * 0x4uL))
#define IRQ_SRC_DMACH119        IRQ_OFFSET(0x0500uL+(119 * 0x4uL))
#define IRQ_SRC_DMACH120        IRQ_OFFSET(0x0500uL+(120 * 0x4uL))
#define IRQ_SRC_DMACH121        IRQ_OFFSET(0x0500uL+(121 * 0x4uL))
#define IRQ_SRC_DMACH122        IRQ_OFFSET(0x0500uL+(122 * 0x4uL))
#define IRQ_SRC_DMACH123        IRQ_OFFSET(0x0500uL+(123 * 0x4uL))
#define IRQ_SRC_DMACH124        IRQ_OFFSET(0x0500uL+(124 * 0x4uL))
#define IRQ_SRC_DMACH125        IRQ_OFFSET(0x0500uL+(125 * 0x4uL))
#define IRQ_SRC_DMACH126        IRQ_OFFSET(0x0500uL+(126 * 0x4uL))
#define IRQ_SRC_DMACH127        IRQ_OFFSET(0x0500uL+(127 * 0x4uL))
#define IRQ_SRC_ETH             IRQ_OFFSET(0x08F0uL)
#define IRQ_SRC_CANINT0         IRQ_OFFSET(0x0900uL+(0 * 0x4uL))
#define IRQ_SRC_CANINT1         IRQ_OFFSET(0x0900uL+(1 * 0x4uL))
#define IRQ_SRC_CANINT2         IRQ_OFFSET(0x0900uL+(2 * 0x4uL))
#define IRQ_SRC_CANINT3         IRQ_OFFSET(0x0900uL+(3 * 0x4uL))
#define IRQ_SRC_CANINT4         IRQ_OFFSET(0x0900uL+(4 * 0x4uL))
#define IRQ_SRC_CANINT5         IRQ_OFFSET(0x0900uL+(5 * 0x4uL))
#define IRQ_SRC_CANINT6         IRQ_OFFSET(0x0900uL+(6 * 0x4uL))
#define IRQ_SRC_CANINT7         IRQ_OFFSET(0x0900uL+(7 * 0x4uL))
#define IRQ_SRC_CANINT8         IRQ_OFFSET(0x0900uL+(8 * 0x4uL))
#define IRQ_SRC_CANINT9         IRQ_OFFSET(0x0900uL+(9 * 0x4uL))
#define IRQ_SRC_CANINT10        IRQ_OFFSET(0x0900uL+(10 * 0x4uL))
#define IRQ_SRC_CANINT11        IRQ_OFFSET(0x0900uL+(11 * 0x4uL))
#define IRQ_SRC_CANINT12        IRQ_OFFSET(0x0900uL+(12 * 0x4uL))
#define IRQ_SRC_CANINT13        IRQ_OFFSET(0x0900uL+(13 * 0x4uL))
#define IRQ_SRC_CANINT14        IRQ_OFFSET(0x0900uL+(14 * 0x4uL))
#define IRQ_SRC_CANINT15        IRQ_OFFSET(0x0900uL+(15 * 0x4uL))
#define IRQ_SRC_CANRINT0        IRQ_OFFSET(0x0940uL+(0 * 0x4uL))
#define IRQ_SRC_CANRINT1        IRQ_OFFSET(0x0940uL+(1 * 0x4uL))
#define IRQ_SRC_CANRINT2        IRQ_OFFSET(0x0940uL+(2 * 0x4uL))
#define IRQ_SRC_CANRINT3        IRQ_OFFSET(0x0940uL+(3 * 0x4uL))
#define IRQ_SRC_CANRINT4        IRQ_OFFSET(0x0940uL+(4 * 0x4uL))
#define IRQ_SRC_CANRINT5        IRQ_OFFSET(0x0940uL+(5 * 0x4uL))
#define IRQ_SRC_CANRINT6        IRQ_OFFSET(0x0940uL+(6 * 0x4uL))
#define IRQ_SRC_CANRINT7        IRQ_OFFSET(0x0940uL+(7 * 0x4uL))
#define IRQ_SRC_VADCG0SR0       IRQ_OFFSET(0x0980uL+(0 * 0x4uL))
#define IRQ_SRC_VADCG0SR1       IRQ_OFFSET(0x0980uL+(1 * 0x4uL))
#define IRQ_SRC_VADCG0SR2       IRQ_OFFSET(0x0980uL+(2 * 0x4uL))
#define IRQ_SRC_VADCG0SR3       IRQ_OFFSET(0x0980uL+(3 * 0x4uL))
#define IRQ_SRC_VADCG1SR0       IRQ_OFFSET(0x0990uL+(0 * 0x4uL))
#define IRQ_SRC_VADCG1SR1       IRQ_OFFSET(0x0990uL+(1 * 0x4uL))
#define IRQ_SRC_VADCG1SR2       IRQ_OFFSET(0x0990uL+(2 * 0x4uL))
#define IRQ_SRC_VADCG1SR3       IRQ_OFFSET(0x0990uL+(3 * 0x4uL))
#define IRQ_SRC_VADCG2SR0       IRQ_OFFSET(0x09A0uL+(0 * 0x4uL))
#define IRQ_SRC_VADCG2SR1       IRQ_OFFSET(0x09A0uL+(1 * 0x4uL))
#define IRQ_SRC_VADCG2SR2       IRQ_OFFSET(0x09A0uL+(2 * 0x4uL))
#define IRQ_SRC_VADCG2SR3       IRQ_OFFSET(0x09A0uL+(3 * 0x4uL))
#define IRQ_SRC_VADCG3SR0       IRQ_OFFSET(0x09B0uL+(0 * 0x4uL))
#define IRQ_SRC_VADCG3SR1       IRQ_OFFSET(0x09B0uL+(1 * 0x4uL))
#define IRQ_SRC_VADCG3SR2       IRQ_OFFSET(0x09B0uL+(2 * 0x4uL))
#define IRQ_SRC_VADCG3SR3       IRQ_OFFSET(0x09B0uL+(3 * 0x4uL))
#define IRQ_SRC_VADCG4SR0       IRQ_OFFSET(0x09C0uL+(0 * 0x4uL))
#define IRQ_SRC_VADCG4SR1       IRQ_OFFSET(0x09C0uL+(1 * 0x4uL))
#define IRQ_SRC_VADCG4SR2       IRQ_OFFSET(0x09C0uL+(2 * 0x4uL))
#define IRQ_SRC_VADCG4SR3       IRQ_OFFSET(0x09C0uL+(3 * 0x4uL))
#define IRQ_SRC_VADCG5SR0       IRQ_OFFSET(0x09D0uL+(0 * 0x4uL))
#define IRQ_SRC_VADCG5SR1       IRQ_OFFSET(0x09D0uL+(1 * 0x4uL))
#define IRQ_SRC_VADCG5SR2       IRQ_OFFSET(0x09D0uL+(2 * 0x4uL))
#define IRQ_SRC_VADCG5SR3       IRQ_OFFSET(0x09D0uL+(3 * 0x4uL))
#define IRQ_SRC_VADCG6SR0       IRQ_OFFSET(0x09E0uL+(0 * 0x4uL))
#define IRQ_SRC_VADCG6SR1       IRQ_OFFSET(0x09E0uL+(1 * 0x4uL))
#define IRQ_SRC_VADCG6SR2       IRQ_OFFSET(0x09E0uL+(2 * 0x4uL))
#define IRQ_SRC_VADCG6SR3       IRQ_OFFSET(0x09E0uL+(3 * 0x4uL))
#define IRQ_SRC_VADCG7SR0       IRQ_OFFSET(0x09F0uL+(0 * 0x4uL))
#define IRQ_SRC_VADCG7SR1       IRQ_OFFSET(0x09F0uL+(1 * 0x4uL))
#define IRQ_SRC_VADCG7SR2       IRQ_OFFSET(0x09F0uL+(2 * 0x4uL))
#define IRQ_SRC_VADCG7SR3       IRQ_OFFSET(0x09F0uL+(3 * 0x4uL))
#define IRQ_SRC_VADCG87SR0      IRQ_OFFSET(0x0A00uL+(0 * 0x4uL))
#define IRQ_SRC_VADCG87SR1      IRQ_OFFSET(0x0A00uL+(1 * 0x4uL))
#define IRQ_SRC_VADCG87SR2      IRQ_OFFSET(0x0A00uL+(2 * 0x4uL))
#define IRQ_SRC_VADCG87SR3      IRQ_OFFSET(0x0A00uL+(3 * 0x4uL))
#define IRQ_SRC_VADCG9SR0       IRQ_OFFSET(0x0A10uL+(0 * 0x4uL))
#define IRQ_SRC_VADCG9SR1       IRQ_OFFSET(0x0A10uL+(1 * 0x4uL))
#define IRQ_SRC_VADCG9SR2       IRQ_OFFSET(0x0A10uL+(2 * 0x4uL))
#define IRQ_SRC_VADCG9SR3       IRQ_OFFSET(0x0A10uL+(3 * 0x4uL))
#define IRQ_SRC_VADCG10SR0      IRQ_OFFSET(0x0A20uL+(0 * 0x4uL))
#define IRQ_SRC_VADCG10SR1      IRQ_OFFSET(0x0A20uL+(1 * 0x4uL))
#define IRQ_SRC_VADCG10SR2      IRQ_OFFSET(0x0A20uL+(2 * 0x4uL))
#define IRQ_SRC_VADCG10SR3      IRQ_OFFSET(0x0A20uL+(3 * 0x4uL))
#define IRQ_SRC_VADCCG0SR0      IRQ_OFFSET(0x0AA0uL+(0 * 0x4uL))
#define IRQ_SRC_VADCCG0SR1      IRQ_OFFSET(0x0AA0uL+(1 * 0x4uL))
#define IRQ_SRC_VADCCG0SR2      IRQ_OFFSET(0x0AA0uL+(2 * 0x4uL))
#define IRQ_SRC_VADCCG0SR3      IRQ_OFFSET(0x0AA0uL+(3 * 0x4uL))
#define IRQ_SRC_VADCCG1SR0      IRQ_OFFSET(0x0AB0uL+(0 * 0x4uL))
#define IRQ_SRC_VADCCG1SR1      IRQ_OFFSET(0x0AB0uL+(1 * 0x4uL))
#define IRQ_SRC_VADCCG1SR2      IRQ_OFFSET(0x0AB0uL+(2 * 0x4uL))
#define IRQ_SRC_VADCCG1SR3      IRQ_OFFSET(0x0AB0uL+(3 * 0x4uL))
#define IRQ_SRC_DSADCSRM0       IRQ_OFFSET(0x0B50uL+(0 * 0x8uL))
#define IRQ_SRC_DSADCSRM1       IRQ_OFFSET(0x0B50uL+(1 * 0x8uL))
#define IRQ_SRC_DSADCSRM2       IRQ_OFFSET(0x0B50uL+(2 * 0x8uL))
#define IRQ_SRC_DSADCSRM3       IRQ_OFFSET(0x0B50uL+(3 * 0x8uL))
#define IRQ_SRC_DSADCSRM4       IRQ_OFFSET(0x0B50uL+(4 * 0x8uL))
#define IRQ_SRC_DSADCSRM5       IRQ_OFFSET(0x0B50uL+(5 * 0x8uL))
#define IRQ_SRC_DSADCSRM6       IRQ_OFFSET(0x0B50uL+(6 * 0x8uL))
#define IRQ_SRC_DSADCSRM7       IRQ_OFFSET(0x0B50uL+(7 * 0x8uL))
#define IRQ_SRC_DSADCSRM8       IRQ_OFFSET(0x0B50uL+(8 * 0x8uL))
#define IRQ_SRC_DSADCSRM9       IRQ_OFFSET(0x0B50uL+(9 * 0x8uL))
#define IRQ_SRC_DSADCSRA0       IRQ_OFFSET(0x0B54uL+(0 * 0x8uL))
#define IRQ_SRC_DSADCSRA1       IRQ_OFFSET(0x0B54uL+(1 * 0x8uL))
#define IRQ_SRC_DSADCSRA2       IRQ_OFFSET(0x0B54uL+(2 * 0x8uL))
#define IRQ_SRC_DSADCSRA3       IRQ_OFFSET(0x0B54uL+(3 * 0x8uL))
#define IRQ_SRC_DSADCSRA4       IRQ_OFFSET(0x0B54uL+(4 * 0x8uL))
#define IRQ_SRC_DSADCSRA5       IRQ_OFFSET(0x0B54uL+(5 * 0x8uL))
#define IRQ_SRC_DSADCSRA6       IRQ_OFFSET(0x0B54uL+(6 * 0x8uL))
#define IRQ_SRC_DSADCSRA7       IRQ_OFFSET(0x0B54uL+(7 * 0x8uL))
#define IRQ_SRC_DSADCSRA8       IRQ_OFFSET(0x0B54uL+(8 * 0x8uL))
#define IRQ_SRC_DSADCSRA9       IRQ_OFFSET(0x0B54uL+(9 * 0x8uL))
#define IRQ_SRC_ERAY0INT0       IRQ_OFFSET(0x0BE0uL+(0 * 0x28uL))
#define IRQ_SRC_ERAY1INT0       IRQ_OFFSET(0x0BE0uL+(1 * 0x28uL))
#define IRQ_SRC_ERAY0INT1       IRQ_OFFSET(0x0BE4uL+(0 * 0x28uL))
#define IRQ_SRC_ERAY1INT1       IRQ_OFFSET(0x0BE4uL+(1 * 0x28uL))
#define IRQ_SRC_ERAY0TINT0      IRQ_OFFSET(0x0BE8uL+(0 * 0x28uL))
#define IRQ_SRC_ERAY1TINT0      IRQ_OFFSET(0x0BE8uL+(1 * 0x28uL))
#define IRQ_SRC_ERAY0TINT1      IRQ_OFFSET(0x0BECuL+(0 * 0x28uL))
#define IRQ_SRC_ERAY1TINT1      IRQ_OFFSET(0x0BECuL+(1 * 0x28uL))
#define IRQ_SRC_ERAY0NDAT0      IRQ_OFFSET(0x0BF0uL+(0 * 0x28uL))
#define IRQ_SRC_ERAY1NDAT0      IRQ_OFFSET(0x0BF0uL+(1 * 0x28uL))
#define IRQ_SRC_ERAY0NDAT1      IRQ_OFFSET(0x0BF4uL+(0 * 0x28uL))
#define IRQ_SRC_ERAY1NDAT1      IRQ_OFFSET(0x0BF4uL+(1 * 0x28uL))
#define IRQ_SRC_ERAY0MBSC0      IRQ_OFFSET(0x0BF8uL+(0 * 0x28uL))
#define IRQ_SRC_ERAY1MBSC0      IRQ_OFFSET(0x0BF8uL+(1 * 0x28uL))
#define IRQ_SRC_ERAY0MBSC1      IRQ_OFFSET(0x0BFCuL+(0 * 0x28uL))
#define IRQ_SRC_ERAY1MBSC1      IRQ_OFFSET(0x0BFCuL+(1 * 0x28uL))
#define IRQ_SRC_ERAY0OBUSY      IRQ_OFFSET(0x0C00uL+(0 * 0x28uL))
#define IRQ_SRC_ERAY1OBUSY      IRQ_OFFSET(0x0C00uL+(1 * 0x28uL))
#define IRQ_SRC_ERAY0IBUSY      IRQ_OFFSET(0x0C04uL+(0 * 0x28uL))
#define IRQ_SRC_ERAY1IBUSY      IRQ_OFFSET(0x0C04uL+(1 * 0x28uL))
#define IRQ_SRC_PMU00           IRQ_OFFSET(0x0C30uL)
#define IRQ_SRC_PMU01           IRQ_OFFSET(0x0C34uL)
#define IRQ_SRC_HSM0            IRQ_OFFSET(0x0CC0uL+(0 * 0x4uL))
#define IRQ_SRC_HSM1            IRQ_OFFSET(0x0CC0uL+(1 * 0x4uL))
#define IRQ_SRC_SCUDTS          IRQ_OFFSET(0x0CD0uL)
#define IRQ_SRC_SCUERU0         IRQ_OFFSET(0x0CD4uL+(0 * 0x4uL))
#define IRQ_SRC_SCUERU1         IRQ_OFFSET(0x0CD4uL+(1 * 0x4uL))
#define IRQ_SRC_SCUERU2         IRQ_OFFSET(0x0CD4uL+(2 * 0x4uL))
#define IRQ_SRC_SCUERU3         IRQ_OFFSET(0x0CD4uL+(3 * 0x4uL))
#define IRQ_SRC_SMU0            IRQ_OFFSET(0x0D10uL+(0 * 0x4uL))
#define IRQ_SRC_SMU1            IRQ_OFFSET(0x0D10uL+(1 * 0x4uL))
#define IRQ_SRC_SMU2            IRQ_OFFSET(0x0D10uL+(2 * 0x4uL))
#define IRQ_SRC_PSI50           IRQ_OFFSET(0x0D30uL+(0 * 0x4uL))
#define IRQ_SRC_PSI51           IRQ_OFFSET(0x0D30uL+(1 * 0x4uL))
#define IRQ_SRC_PSI52           IRQ_OFFSET(0x0D30uL+(2 * 0x4uL))
#define IRQ_SRC_PSI53           IRQ_OFFSET(0x0D30uL+(3 * 0x4uL))
#define IRQ_SRC_PSI54           IRQ_OFFSET(0x0D30uL+(4 * 0x4uL))
#define IRQ_SRC_PSI55           IRQ_OFFSET(0x0D30uL+(5 * 0x4uL))
#define IRQ_SRC_PSI56           IRQ_OFFSET(0x0D30uL+(6 * 0x4uL))
#define IRQ_SRC_PSI57           IRQ_OFFSET(0x0D30uL+(7 * 0x4uL))
#define IRQ_SRC_DAMLI0          IRQ_OFFSET(0x0D70uL)
#define IRQ_SRC_DAMRI0          IRQ_OFFSET(0x0D74uL)
#define IRQ_SRC_DAMLI1          IRQ_OFFSET(0x0D78uL)
#define IRQ_SRC_DAMRI1          IRQ_OFFSET(0x0D7CuL)
#define IRQ_SRC_DAMDR           IRQ_OFFSET(0x0D80uL)
#define IRQ_SRC_DAMERR          IRQ_OFFSET(0x0D84uL)
#define IRQ_SRC_CIFMI           IRQ_OFFSET(0x0DA0uL)
#define IRQ_SRC_CIFMIEP         IRQ_OFFSET(0x0DA4uL)
#define IRQ_SRC_CIFISP          IRQ_OFFSET(0x0DA8uL)
#define IRQ_SRC_CIFMJPEG        IRQ_OFFSET(0x0DACuL)
#define IRQ_SRC_LMU             IRQ_OFFSET(0x0DE0uL)
#define IRQ_SRC_PSI5S0          IRQ_OFFSET(0x0DF0uL+(0 * 0x4uL))
#define IRQ_SRC_PSI5S1          IRQ_OFFSET(0x0DF0uL+(1 * 0x4uL))
#define IRQ_SRC_PSI5S2          IRQ_OFFSET(0x0DF0uL+(2 * 0x4uL))
#define IRQ_SRC_PSI5S3          IRQ_OFFSET(0x0DF0uL+(3 * 0x4uL))
#define IRQ_SRC_PSI5S4          IRQ_OFFSET(0x0DF0uL+(4 * 0x4uL))
#define IRQ_SRC_PSI5S5          IRQ_OFFSET(0x0DF0uL+(5 * 0x4uL))
#define IRQ_SRC_PSI5S6          IRQ_OFFSET(0x0DF0uL+(6 * 0x4uL))
#define IRQ_SRC_PSI5S7          IRQ_OFFSET(0x0DF0uL+(7 * 0x4uL))
#define IRQ_SRC_FFTDONE         IRQ_OFFSET(0x0FC0uL)
#define IRQ_SRC_FFTERR          IRQ_OFFSET(0x0FC4uL)
#define IRQ_SRC_FFTRFS          IRQ_OFFSET(0x0FC8uL)
#define IRQ_SRC_RESERVED0       IRQ_OFFSET(0x0FCCuL)
#define IRQ_SRC_GPSR00          IRQ_OFFSET(0x1000uL+(0 * 0x4uL))
#define IRQ_SRC_GPSR01          IRQ_OFFSET(0x1000uL+(1 * 0x4uL))
#define IRQ_SRC_GPSR02          IRQ_OFFSET(0x1000uL+(2 * 0x4uL))
#define IRQ_SRC_GPSR03          IRQ_OFFSET(0x1000uL+(3 * 0x4uL))
#define IRQ_SRC_GPSR10          IRQ_OFFSET(0x1020uL+(0 * 0x4uL))
#define IRQ_SRC_GPSR11          IRQ_OFFSET(0x1020uL+(1 * 0x4uL))
#define IRQ_SRC_GPSR12          IRQ_OFFSET(0x1020uL+(2 * 0x4uL))
#define IRQ_SRC_GPSR13          IRQ_OFFSET(0x1020uL+(3 * 0x4uL))
#define IRQ_SRC_GPSR20          IRQ_OFFSET(0x1040uL+(0 * 0x4uL))
#define IRQ_SRC_GPSR21          IRQ_OFFSET(0x1040uL+(1 * 0x4uL))
#define IRQ_SRC_GPSR22          IRQ_OFFSET(0x1040uL+(2 * 0x4uL))
#define IRQ_SRC_GPSR23          IRQ_OFFSET(0x1040uL+(3 * 0x4uL))
#define IRQ_SRC_GTMAEIIRQ       IRQ_OFFSET(0x1600uL)
#define IRQ_SRC_GTMARUIRQ0      IRQ_OFFSET(0x1604uL+(0 * 0x4uL))
#define IRQ_SRC_GTMARUIRQ1      IRQ_OFFSET(0x1604uL+(1 * 0x4uL))
#define IRQ_SRC_GTMARUIRQ2      IRQ_OFFSET(0x1604uL+(2 * 0x4uL))
#define IRQ_SRC_GTMBRCIRQ       IRQ_OFFSET(0x1614uL)
#define IRQ_SRC_GTMCMPIRQ       IRQ_OFFSET(0x1618uL)
#define IRQ_SRC_GTMSPE0IR       IRQ_OFFSET(0x161CuL+(0 * 0x4uL))
#define IRQ_SRC_GTMSPE1IR       IRQ_OFFSET(0x161CuL+(1 * 0x4uL))
#define IRQ_SRC_GTMSPE2IR       IRQ_OFFSET(0x161CuL+(2 * 0x4uL))
#define IRQ_SRC_GTMSPE3IR       IRQ_OFFSET(0x161CuL+(3 * 0x4uL))
#define IRQ_SRC_GTMPSM00        IRQ_OFFSET(0x162CuL+(0 * 0x4uL))
#define IRQ_SRC_GTMPSM01        IRQ_OFFSET(0x162CuL+(1 * 0x4uL))
#define IRQ_SRC_GTMPSM02        IRQ_OFFSET(0x162CuL+(2 * 0x4uL))
#define IRQ_SRC_GTMPSM03        IRQ_OFFSET(0x162CuL+(3 * 0x4uL))
#define IRQ_SRC_GTMPSM04        IRQ_OFFSET(0x162CuL+(4 * 0x4uL))
#define IRQ_SRC_GTMPSM05        IRQ_OFFSET(0x162CuL+(5 * 0x4uL))
#define IRQ_SRC_GTMPSM06        IRQ_OFFSET(0x162CuL+(6 * 0x4uL))
#define IRQ_SRC_GTMPSM07        IRQ_OFFSET(0x162CuL+(7 * 0x4uL))
#define IRQ_SRC_GTMPSM10        IRQ_OFFSET(0x164CuL+(0 * 0x4uL))
#define IRQ_SRC_GTMPSM11        IRQ_OFFSET(0x164CuL+(1 * 0x4uL))
#define IRQ_SRC_GTMPSM12        IRQ_OFFSET(0x164CuL+(2 * 0x4uL))
#define IRQ_SRC_GTMPSM13        IRQ_OFFSET(0x164CuL+(3 * 0x4uL))
#define IRQ_SRC_GTMPSM14        IRQ_OFFSET(0x164CuL+(4 * 0x4uL))
#define IRQ_SRC_GTMPSM15        IRQ_OFFSET(0x164CuL+(5 * 0x4uL))
#define IRQ_SRC_GTMPSM16        IRQ_OFFSET(0x164CuL+(6 * 0x4uL))
#define IRQ_SRC_GTMPSM17        IRQ_OFFSET(0x164CuL+(7 * 0x4uL))
#define IRQ_SRC_GTMDPLL0        IRQ_OFFSET(0x16A4uL+(0 * 0x4uL))
#define IRQ_SRC_GTMDPLL1        IRQ_OFFSET(0x16A4uL+(1 * 0x4uL))
#define IRQ_SRC_GTMDPLL2        IRQ_OFFSET(0x16A4uL+(2 * 0x4uL))
#define IRQ_SRC_GTMDPLL3        IRQ_OFFSET(0x16A4uL+(3 * 0x4uL))
#define IRQ_SRC_GTMDPLL4        IRQ_OFFSET(0x16A4uL+(4 * 0x4uL))
#define IRQ_SRC_GTMDPLL5        IRQ_OFFSET(0x16A4uL+(5 * 0x4uL))
#define IRQ_SRC_GTMDPLL6        IRQ_OFFSET(0x16A4uL+(6 * 0x4uL))
#define IRQ_SRC_GTMDPLL7        IRQ_OFFSET(0x16A4uL+(7 * 0x4uL))
#define IRQ_SRC_GTMDPLL8        IRQ_OFFSET(0x16A4uL+(8 * 0x4uL))
#define IRQ_SRC_GTMDPLL9        IRQ_OFFSET(0x16A4uL+(9 * 0x4uL))
#define IRQ_SRC_GTMDPLL10       IRQ_OFFSET(0x16A4uL+(10 * 0x4uL))
#define IRQ_SRC_GTMDPLL11       IRQ_OFFSET(0x16A4uL+(11 * 0x4uL))
#define IRQ_SRC_GTMDPLL12       IRQ_OFFSET(0x16A4uL+(12 * 0x4uL))
#define IRQ_SRC_GTMDPLL13       IRQ_OFFSET(0x16A4uL+(13 * 0x4uL))
#define IRQ_SRC_GTMDPLL14       IRQ_OFFSET(0x16A4uL+(14 * 0x4uL))
#define IRQ_SRC_GTMDPLL15       IRQ_OFFSET(0x16A4uL+(15 * 0x4uL))
#define IRQ_SRC_GTMDPLL16       IRQ_OFFSET(0x16A4uL+(16 * 0x4uL))
#define IRQ_SRC_GTMDPLL17       IRQ_OFFSET(0x16A4uL+(17 * 0x4uL))
#define IRQ_SRC_GTMDPLL18       IRQ_OFFSET(0x16A4uL+(18 * 0x4uL))
#define IRQ_SRC_GTMDPLL19       IRQ_OFFSET(0x16A4uL+(19 * 0x4uL))
#define IRQ_SRC_GTMDPLL20       IRQ_OFFSET(0x16A4uL+(20 * 0x4uL))
#define IRQ_SRC_GTMDPLL21       IRQ_OFFSET(0x16A4uL+(21 * 0x4uL))
#define IRQ_SRC_GTMDPLL22       IRQ_OFFSET(0x16A4uL+(22 * 0x4uL))
#define IRQ_SRC_GTMDPLL23       IRQ_OFFSET(0x16A4uL+(23 * 0x4uL))
#define IRQ_SRC_GTMDPLL24       IRQ_OFFSET(0x16A4uL+(24 * 0x4uL))
#define IRQ_SRC_GTMDPLL25       IRQ_OFFSET(0x16A4uL+(25 * 0x4uL))
#define IRQ_SRC_GTMDPLL26       IRQ_OFFSET(0x16A4uL+(26 * 0x4uL))
#define IRQ_SRC_GTMERR          IRQ_OFFSET(0x1770uL)
#define IRQ_SRC_GTMTIM00        IRQ_OFFSET(0x1780uL+(0 * 0x4uL))
#define IRQ_SRC_GTMTIM01        IRQ_OFFSET(0x1780uL+(1 * 0x4uL))
#define IRQ_SRC_GTMTIM02        IRQ_OFFSET(0x1780uL+(2 * 0x4uL))
#define IRQ_SRC_GTMTIM03        IRQ_OFFSET(0x1780uL+(3 * 0x4uL))
#define IRQ_SRC_GTMTIM04        IRQ_OFFSET(0x1780uL+(4 * 0x4uL))
#define IRQ_SRC_GTMTIM05        IRQ_OFFSET(0x1780uL+(5 * 0x4uL))
#define IRQ_SRC_GTMTIM06        IRQ_OFFSET(0x1780uL+(6 * 0x4uL))
#define IRQ_SRC_GTMTIM07        IRQ_OFFSET(0x1780uL+(7 * 0x4uL))
#define IRQ_SRC_GTMTIM10        IRQ_OFFSET(0x17A0uL+(0 * 0x4uL))
#define IRQ_SRC_GTMTIM11        IRQ_OFFSET(0x17A0uL+(1 * 0x4uL))
#define IRQ_SRC_GTMTIM12        IRQ_OFFSET(0x17A0uL+(2 * 0x4uL))
#define IRQ_SRC_GTMTIM13        IRQ_OFFSET(0x17A0uL+(3 * 0x4uL))
#define IRQ_SRC_GTMTIM14        IRQ_OFFSET(0x17A0uL+(4 * 0x4uL))
#define IRQ_SRC_GTMTIM15        IRQ_OFFSET(0x17A0uL+(5 * 0x4uL))
#define IRQ_SRC_GTMTIM16        IRQ_OFFSET(0x17A0uL+(6 * 0x4uL))
#define IRQ_SRC_GTMTIM17        IRQ_OFFSET(0x17A0uL+(7 * 0x4uL))
#define IRQ_SRC_GTMTIM20        IRQ_OFFSET(0x17C0uL+(0 * 0x4uL))
#define IRQ_SRC_GTMTIM21        IRQ_OFFSET(0x17C0uL+(1 * 0x4uL))
#define IRQ_SRC_GTMTIM22        IRQ_OFFSET(0x17C0uL+(2 * 0x4uL))
#define IRQ_SRC_GTMTIM23        IRQ_OFFSET(0x17C0uL+(3 * 0x4uL))
#define IRQ_SRC_GTMTIM24        IRQ_OFFSET(0x17C0uL+(4 * 0x4uL))
#define IRQ_SRC_GTMTIM25        IRQ_OFFSET(0x17C0uL+(5 * 0x4uL))
#define IRQ_SRC_GTMTIM26        IRQ_OFFSET(0x17C0uL+(6 * 0x4uL))
#define IRQ_SRC_GTMTIM27        IRQ_OFFSET(0x17C0uL+(7 * 0x4uL))
#define IRQ_SRC_GTMTIM30        IRQ_OFFSET(0x17E0uL+(0 * 0x4uL))
#define IRQ_SRC_GTMTIM31        IRQ_OFFSET(0x17E0uL+(1 * 0x4uL))
#define IRQ_SRC_GTMTIM32        IRQ_OFFSET(0x17E0uL+(2 * 0x4uL))
#define IRQ_SRC_GTMTIM33        IRQ_OFFSET(0x17E0uL+(3 * 0x4uL))
#define IRQ_SRC_GTMTIM34        IRQ_OFFSET(0x17E0uL+(4 * 0x4uL))
#define IRQ_SRC_GTMTIM35        IRQ_OFFSET(0x17E0uL+(5 * 0x4uL))
#define IRQ_SRC_GTMTIM36        IRQ_OFFSET(0x17E0uL+(6 * 0x4uL))
#define IRQ_SRC_GTMTIM37        IRQ_OFFSET(0x17E0uL+(7 * 0x4uL))
#define IRQ_SRC_GTMTIM40        IRQ_OFFSET(0x1800uL+(0 * 0x4uL))
#define IRQ_SRC_GTMTIM41        IRQ_OFFSET(0x1800uL+(1 * 0x4uL))
#define IRQ_SRC_GTMTIM42        IRQ_OFFSET(0x1800uL+(2 * 0x4uL))
#define IRQ_SRC_GTMTIM43        IRQ_OFFSET(0x1800uL+(3 * 0x4uL))
#define IRQ_SRC_GTMTIM44        IRQ_OFFSET(0x1800uL+(4 * 0x4uL))
#define IRQ_SRC_GTMTIM45        IRQ_OFFSET(0x1800uL+(5 * 0x4uL))
#define IRQ_SRC_GTMTIM46        IRQ_OFFSET(0x1800uL+(6 * 0x4uL))
#define IRQ_SRC_GTMTIM47        IRQ_OFFSET(0x1800uL+(7 * 0x4uL))
#define IRQ_SRC_GTMTIM50        IRQ_OFFSET(0x1820uL+(0 * 0x4uL))
#define IRQ_SRC_GTMTIM51        IRQ_OFFSET(0x1820uL+(1 * 0x4uL))
#define IRQ_SRC_GTMTIM52        IRQ_OFFSET(0x1820uL+(2 * 0x4uL))
#define IRQ_SRC_GTMTIM53        IRQ_OFFSET(0x1820uL+(3 * 0x4uL))
#define IRQ_SRC_GTMTIM54        IRQ_OFFSET(0x1820uL+(4 * 0x4uL))
#define IRQ_SRC_GTMTIM55        IRQ_OFFSET(0x1820uL+(5 * 0x4uL))
#define IRQ_SRC_GTMTIM56        IRQ_OFFSET(0x1820uL+(6 * 0x4uL))
#define IRQ_SRC_GTMTIM57        IRQ_OFFSET(0x1820uL+(7 * 0x4uL))
#define IRQ_SRC_GTMMCS00        IRQ_OFFSET(0x1980uL+(0 * 0x4uL))
#define IRQ_SRC_GTMMCS01        IRQ_OFFSET(0x1980uL+(1 * 0x4uL))
#define IRQ_SRC_GTMMCS02        IRQ_OFFSET(0x1980uL+(2 * 0x4uL))
#define IRQ_SRC_GTMMCS03        IRQ_OFFSET(0x1980uL+(3 * 0x4uL))
#define IRQ_SRC_GTMMCS04        IRQ_OFFSET(0x1980uL+(4 * 0x4uL))
#define IRQ_SRC_GTMMCS05        IRQ_OFFSET(0x1980uL+(5 * 0x4uL))
#define IRQ_SRC_GTMMCS06        IRQ_OFFSET(0x1980uL+(6 * 0x4uL))
#define IRQ_SRC_GTMMCS07        IRQ_OFFSET(0x1980uL+(7 * 0x4uL))
#define IRQ_SRC_GTMMCS10        IRQ_OFFSET(0x19A0uL+(0 * 0x4uL))
#define IRQ_SRC_GTMMCS11        IRQ_OFFSET(0x19A0uL+(1 * 0x4uL))
#define IRQ_SRC_GTMMCS12        IRQ_OFFSET(0x19A0uL+(2 * 0x4uL))
#define IRQ_SRC_GTMMCS13        IRQ_OFFSET(0x19A0uL+(3 * 0x4uL))
#define IRQ_SRC_GTMMCS14        IRQ_OFFSET(0x19A0uL+(4 * 0x4uL))
#define IRQ_SRC_GTMMCS15        IRQ_OFFSET(0x19A0uL+(5 * 0x4uL))
#define IRQ_SRC_GTMMCS16        IRQ_OFFSET(0x19A0uL+(6 * 0x4uL))
#define IRQ_SRC_GTMMCS17        IRQ_OFFSET(0x19A0uL+(7 * 0x4uL))
#define IRQ_SRC_GTMMCS20        IRQ_OFFSET(0x19C0uL+(0 * 0x4uL))
#define IRQ_SRC_GTMMCS21        IRQ_OFFSET(0x19C0uL+(1 * 0x4uL))
#define IRQ_SRC_GTMMCS22        IRQ_OFFSET(0x19C0uL+(2 * 0x4uL))
#define IRQ_SRC_GTMMCS23        IRQ_OFFSET(0x19C0uL+(3 * 0x4uL))
#define IRQ_SRC_GTMMCS24        IRQ_OFFSET(0x19C0uL+(4 * 0x4uL))
#define IRQ_SRC_GTMMCS25        IRQ_OFFSET(0x19C0uL+(5 * 0x4uL))
#define IRQ_SRC_GTMMCS26        IRQ_OFFSET(0x19C0uL+(6 * 0x4uL))
#define IRQ_SRC_GTMMCS27        IRQ_OFFSET(0x19C0uL+(7 * 0x4uL))
#define IRQ_SRC_GTMMCS30        IRQ_OFFSET(0x19E0uL+(0 * 0x4uL))
#define IRQ_SRC_GTMMCS31        IRQ_OFFSET(0x19E0uL+(1 * 0x4uL))
#define IRQ_SRC_GTMMCS32        IRQ_OFFSET(0x19E0uL+(2 * 0x4uL))
#define IRQ_SRC_GTMMCS33        IRQ_OFFSET(0x19E0uL+(3 * 0x4uL))
#define IRQ_SRC_GTMMCS34        IRQ_OFFSET(0x19E0uL+(4 * 0x4uL))
#define IRQ_SRC_GTMMCS35        IRQ_OFFSET(0x19E0uL+(5 * 0x4uL))
#define IRQ_SRC_GTMMCS36        IRQ_OFFSET(0x19E0uL+(6 * 0x4uL))
#define IRQ_SRC_GTMMCS37        IRQ_OFFSET(0x19E0uL+(7 * 0x4uL))
#define IRQ_SRC_GTMMCS40        IRQ_OFFSET(0x1A00uL+(0 * 0x4uL))
#define IRQ_SRC_GTMMCS41        IRQ_OFFSET(0x1A00uL+(1 * 0x4uL))
#define IRQ_SRC_GTMMCS42        IRQ_OFFSET(0x1A00uL+(2 * 0x4uL))
#define IRQ_SRC_GTMMCS43        IRQ_OFFSET(0x1A00uL+(3 * 0x4uL))
#define IRQ_SRC_GTMMCS44        IRQ_OFFSET(0x1A00uL+(4 * 0x4uL))
#define IRQ_SRC_GTMMCS45        IRQ_OFFSET(0x1A00uL+(5 * 0x4uL))
#define IRQ_SRC_GTMMCS46        IRQ_OFFSET(0x1A00uL+(6 * 0x4uL))
#define IRQ_SRC_GTMMCS47        IRQ_OFFSET(0x1A00uL+(7 * 0x4uL))
#define IRQ_SRC_GTMMCS50        IRQ_OFFSET(0x1A20uL+(0 * 0x4uL))
#define IRQ_SRC_GTMMCS51        IRQ_OFFSET(0x1A20uL+(1 * 0x4uL))
#define IRQ_SRC_GTMMCS52        IRQ_OFFSET(0x1A20uL+(2 * 0x4uL))
#define IRQ_SRC_GTMMCS53        IRQ_OFFSET(0x1A20uL+(3 * 0x4uL))
#define IRQ_SRC_GTMMCS54        IRQ_OFFSET(0x1A20uL+(4 * 0x4uL))
#define IRQ_SRC_GTMMCS55        IRQ_OFFSET(0x1A20uL+(5 * 0x4uL))
#define IRQ_SRC_GTMMCS56        IRQ_OFFSET(0x1A20uL+(6 * 0x4uL))
#define IRQ_SRC_GTMMCS57        IRQ_OFFSET(0x1A20uL+(7 * 0x4uL))
#define IRQ_SRC_GTMTOM00        IRQ_OFFSET(0x1B80uL+(0 * 0x4uL))
#define IRQ_SRC_GTMTOM01        IRQ_OFFSET(0x1B80uL+(1 * 0x4uL))
#define IRQ_SRC_GTMTOM02        IRQ_OFFSET(0x1B80uL+(2 * 0x4uL))
#define IRQ_SRC_GTMTOM03        IRQ_OFFSET(0x1B80uL+(3 * 0x4uL))
#define IRQ_SRC_GTMTOM04        IRQ_OFFSET(0x1B80uL+(4 * 0x4uL))
#define IRQ_SRC_GTMTOM05        IRQ_OFFSET(0x1B80uL+(5 * 0x4uL))
#define IRQ_SRC_GTMTOM06        IRQ_OFFSET(0x1B80uL+(6 * 0x4uL))
#define IRQ_SRC_GTMTOM07        IRQ_OFFSET(0x1B80uL+(7 * 0x4uL))
#define IRQ_SRC_GTMTOM10        IRQ_OFFSET(0x1BA0uL+(0 * 0x4uL))
#define IRQ_SRC_GTMTOM11        IRQ_OFFSET(0x1BA0uL+(1 * 0x4uL))
#define IRQ_SRC_GTMTOM12        IRQ_OFFSET(0x1BA0uL+(2 * 0x4uL))
#define IRQ_SRC_GTMTOM13        IRQ_OFFSET(0x1BA0uL+(3 * 0x4uL))
#define IRQ_SRC_GTMTOM14        IRQ_OFFSET(0x1BA0uL+(4 * 0x4uL))
#define IRQ_SRC_GTMTOM15        IRQ_OFFSET(0x1BA0uL+(5 * 0x4uL))
#define IRQ_SRC_GTMTOM16        IRQ_OFFSET(0x1BA0uL+(6 * 0x4uL))
#define IRQ_SRC_GTMTOM17        IRQ_OFFSET(0x1BA0uL+(7 * 0x4uL))
#define IRQ_SRC_GTMTOM20        IRQ_OFFSET(0x1BC0uL+(0 * 0x4uL))
#define IRQ_SRC_GTMTOM21        IRQ_OFFSET(0x1BC0uL+(1 * 0x4uL))
#define IRQ_SRC_GTMTOM22        IRQ_OFFSET(0x1BC0uL+(2 * 0x4uL))
#define IRQ_SRC_GTMTOM23        IRQ_OFFSET(0x1BC0uL+(3 * 0x4uL))
#define IRQ_SRC_GTMTOM24        IRQ_OFFSET(0x1BC0uL+(4 * 0x4uL))
#define IRQ_SRC_GTMTOM25        IRQ_OFFSET(0x1BC0uL+(5 * 0x4uL))
#define IRQ_SRC_GTMTOM26        IRQ_OFFSET(0x1BC0uL+(6 * 0x4uL))
#define IRQ_SRC_GTMTOM27        IRQ_OFFSET(0x1BC0uL+(7 * 0x4uL))
#define IRQ_SRC_GTMTOM30        IRQ_OFFSET(0x1BE0uL+(0 * 0x4uL))
#define IRQ_SRC_GTMTOM31        IRQ_OFFSET(0x1BE0uL+(1 * 0x4uL))
#define IRQ_SRC_GTMTOM32        IRQ_OFFSET(0x1BE0uL+(2 * 0x4uL))
#define IRQ_SRC_GTMTOM33        IRQ_OFFSET(0x1BE0uL+(3 * 0x4uL))
#define IRQ_SRC_GTMTOM34        IRQ_OFFSET(0x1BE0uL+(4 * 0x4uL))
#define IRQ_SRC_GTMTOM35        IRQ_OFFSET(0x1BE0uL+(5 * 0x4uL))
#define IRQ_SRC_GTMTOM36        IRQ_OFFSET(0x1BE0uL+(6 * 0x4uL))
#define IRQ_SRC_GTMTOM37        IRQ_OFFSET(0x1BE0uL+(7 * 0x4uL))
#define IRQ_SRC_GTMTOM40        IRQ_OFFSET(0x1C00uL+(0 * 0x4uL))
#define IRQ_SRC_GTMTOM41        IRQ_OFFSET(0x1C00uL+(1 * 0x4uL))
#define IRQ_SRC_GTMTOM42        IRQ_OFFSET(0x1C00uL+(2 * 0x4uL))
#define IRQ_SRC_GTMTOM43        IRQ_OFFSET(0x1C00uL+(3 * 0x4uL))
#define IRQ_SRC_GTMTOM44        IRQ_OFFSET(0x1C00uL+(4 * 0x4uL))
#define IRQ_SRC_GTMTOM45        IRQ_OFFSET(0x1C00uL+(5 * 0x4uL))
#define IRQ_SRC_GTMTOM46        IRQ_OFFSET(0x1C00uL+(6 * 0x4uL))
#define IRQ_SRC_GTMTOM47        IRQ_OFFSET(0x1C00uL+(7 * 0x4uL))
#define IRQ_SRC_GTMATOM00       IRQ_OFFSET(0x1D80uL+(0 * 0x4uL))
#define IRQ_SRC_GTMATOM01       IRQ_OFFSET(0x1D80uL+(1 * 0x4uL))
#define IRQ_SRC_GTMATOM02       IRQ_OFFSET(0x1D80uL+(2 * 0x4uL))
#define IRQ_SRC_GTMATOM03       IRQ_OFFSET(0x1D80uL+(3 * 0x4uL))
#define IRQ_SRC_GTMATOM10       IRQ_OFFSET(0x1D90uL+(0 * 0x4uL))
#define IRQ_SRC_GTMATOM11       IRQ_OFFSET(0x1D90uL+(1 * 0x4uL))
#define IRQ_SRC_GTMATOM12       IRQ_OFFSET(0x1D90uL+(2 * 0x4uL))
#define IRQ_SRC_GTMATOM13       IRQ_OFFSET(0x1D90uL+(3 * 0x4uL))
#define IRQ_SRC_GTMATOM20       IRQ_OFFSET(0x1DA0uL+(0 * 0x4uL))
#define IRQ_SRC_GTMATOM21       IRQ_OFFSET(0x1DA0uL+(1 * 0x4uL))
#define IRQ_SRC_GTMATOM22       IRQ_OFFSET(0x1DA0uL+(2 * 0x4uL))
#define IRQ_SRC_GTMATOM23       IRQ_OFFSET(0x1DA0uL+(3 * 0x4uL))
#define IRQ_SRC_GTMATOM30       IRQ_OFFSET(0x1DB0uL+(0 * 0x4uL))
#define IRQ_SRC_GTMATOM31       IRQ_OFFSET(0x1DB0uL+(1 * 0x4uL))
#define IRQ_SRC_GTMATOM32       IRQ_OFFSET(0x1DB0uL+(2 * 0x4uL))
#define IRQ_SRC_GTMATOM33       IRQ_OFFSET(0x1DB0uL+(3 * 0x4uL))
#define IRQ_SRC_GTMATOM40       IRQ_OFFSET(0x1DC0uL+(0 * 0x4uL))
#define IRQ_SRC_GTMATOM41       IRQ_OFFSET(0x1DC0uL+(1 * 0x4uL))
#define IRQ_SRC_GTMATOM42       IRQ_OFFSET(0x1DC0uL+(2 * 0x4uL))
#define IRQ_SRC_GTMATOM43       IRQ_OFFSET(0x1DC0uL+(3 * 0x4uL))
#define IRQ_SRC_GTMATOM50       IRQ_OFFSET(0x1DD0uL+(0 * 0x4uL))
#define IRQ_SRC_GTMATOM51       IRQ_OFFSET(0x1DD0uL+(1 * 0x4uL))
#define IRQ_SRC_GTMATOM52       IRQ_OFFSET(0x1DD0uL+(2 * 0x4uL))
#define IRQ_SRC_GTMATOM53       IRQ_OFFSET(0x1DD0uL+(3 * 0x4uL))
#define IRQ_SRC_GTMATOM60       IRQ_OFFSET(0x1DE0uL+(0 * 0x4uL))
#define IRQ_SRC_GTMATOM61       IRQ_OFFSET(0x1DE0uL+(1 * 0x4uL))
#define IRQ_SRC_GTMATOM62       IRQ_OFFSET(0x1DE0uL+(2 * 0x4uL))
#define IRQ_SRC_GTMATOM63       IRQ_OFFSET(0x1DE0uL+(3 * 0x4uL))
#define IRQ_SRC_GTMATOM70       IRQ_OFFSET(0x1DF0uL+(0 * 0x4uL))
#define IRQ_SRC_GTMATOM71       IRQ_OFFSET(0x1DF0uL+(1 * 0x4uL))
#define IRQ_SRC_GTMATOM72       IRQ_OFFSET(0x1DF0uL+(2 * 0x4uL))
#define IRQ_SRC_GTMATOM73       IRQ_OFFSET(0x1DF0uL+(3 * 0x4uL))
#define IRQ_SRC_GTMATOM80       IRQ_OFFSET(0x1E00uL+(0 * 0x4uL))
#define IRQ_SRC_GTMATOM81       IRQ_OFFSET(0x1E00uL+(1 * 0x4uL))
#define IRQ_SRC_GTMATOM82       IRQ_OFFSET(0x1E00uL+(2 * 0x4uL))
#define IRQ_SRC_GTMATOM83       IRQ_OFFSET(0x1E00uL+(3 * 0x4uL))
#define IRQ_SRC_GTMMCSW00       IRQ_OFFSET(0x1F00uL+(0 * 0x4uL))
#define IRQ_SRC_GTMMCSW01       IRQ_OFFSET(0x1F00uL+(1 * 0x4uL))
#define IRQ_SRC_GTMMCSW02       IRQ_OFFSET(0x1F00uL+(2 * 0x4uL))
#define IRQ_SRC_GTMMCSW03       IRQ_OFFSET(0x1F00uL+(3 * 0x4uL))
#define IRQ_SRC_GTMMCSW04       IRQ_OFFSET(0x1F00uL+(4 * 0x4uL))
#define IRQ_SRC_GTMMCSW05       IRQ_OFFSET(0x1F00uL+(5 * 0x4uL))
#define IRQ_SRC_GTMMCSW06       IRQ_OFFSET(0x1F00uL+(6 * 0x4uL))
#define IRQ_SRC_GTMMCSW10       IRQ_OFFSET(0x1F40uL+(0 * 0x4uL))
#define IRQ_SRC_GTMMCSW11       IRQ_OFFSET(0x1F40uL+(1 * 0x4uL))
#define IRQ_SRC_GTMMCSW12       IRQ_OFFSET(0x1F40uL+(2 * 0x4uL))
#define IRQ_SRC_GTMMCSW13       IRQ_OFFSET(0x1F40uL+(3 * 0x4uL))
#define IRQ_SRC_GTMMCSW14       IRQ_OFFSET(0x1F40uL+(4 * 0x4uL))
#define IRQ_SRC_GTMMCSW15       IRQ_OFFSET(0x1F40uL+(5 * 0x4uL))
typedef uint16 IrqType;

#define NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS		2004

#define IRQ_SRPN_CNT							512

#define IRQ_SRPN_TOP_PRIO                       256uL

 /* Offset from start of exceptions to interrupts
  * Exceptions have negative offsets while interrupts have positive
  */
 #define IRQ_INTERRUPT_OFFSET  0

 #define Irq_SOI()

 /* Total number of interrupts and exceptions
  */

 typedef enum {
    CLOCK_CPU0,
    CLOCK_CPU1,
    CLOCK_CPU2,
    CLOCK_STM,
 } Mcu_Arc_PeriperalClock_t;


 typedef enum {
     CPU_0 = 0,
     CPU_1 = 1,
     CPU_2 = 2,
 } Cpu_t;

#endif /* IRQ_TC297_H_ */
